Optimizing Two-Phase Clock Generators for Adiabatic Logic Circuits

Verilog Modeling for a Two-Phase Clock Generator with Quarter-Cycle Offset

Two-phase non-overlapping clocks are crucial for driving switched-capacitor circuits, registers, and dynamic logic systems. A quarter-cycle offset introduces a strict 90-degree phase shift between the two clock signals ( CLKAcap C cap L cap K sub cap A CLKBcap C cap L cap K sub cap B

). Modeling this behavior precisely in Verilog requires careful handling of timing dependencies to avoid race conditions and clock glitches. Design Architecture and Specifications

To achieve an exact quarter-cycle (90°) offset, the input master clock ( CLKincap C cap L cap K sub i n end-sub

) must run at a higher frequency than the target output clocks. The most reliable digital approach utilizes a frequency divider driven by a master clock running at 2x the target frequency. Timing Parameters Master Clock ( CLKincap C cap L cap K sub i n end-sub ): Period = T Output Clocks ( ): Period = 2T

Phase Offset: T/2 (which equals 90° or a quarter-cycle of the output clock period)

CLK_in : |¯¯||¯¯||¯¯||¯¯||¯¯| CLK_A : _|¯¯¯¯¯¯¯¯|_____|¯¯¯¯¯¯¯¯| CLK_B : ____|¯¯¯¯¯¯¯¯|_____|¯¯¯¯¯¯ <–T–> (Master Period) <—-2T—-> (Output Period) <-T/2-> (Quarter-Cycle Offset) Use code with caution. Verilog Implementation

The following Register Transfer Level (RTL) code implements the generator using a 2-bit Johnson counter or state sequencer running on both edges of the master clock, or a single edge of a double-frequency clock. This implementation uses the rising and falling edges of a 2x master clock to safely derive the quadrature phases without glitch-prone combinational logic.

module two_phase_clk_gen ( input wire clk_in, // Master clock (2x output frequency) input wire rst_n, // Active-low asynchronous reset output reg clk_a, // Phase A output clock output reg clk_b // Phase B output clock (90-degree offset) ); // Internal state register reg [1:0] count; // Sequential logic for the state counter always @(posedge clk_in or negedge rst_n) begin if (!rst_n) begin count <= 2’b00; end else begin count <= count + 1’b1; end end // Glitch-free registered outputs always @(posedge clk_in or negedge rst_n) begin if (!rst_n) begin clk_a <= 1’b0; clk_b <= 1’b0; end else begin case (count) 2’b00: begin clk_a <= 1’b1; clk_b <= 1’b0; end 2’b01: begin clk_a <= 1’b1; clk_b <= 1’b1; end 2’b10: begin clk_a <= 1’b0; clk_b <= 1’b1; end 2’b11: begin clk_a <= 1’b0; clk_b <= 1’b0; end endcase end end endmodule Use code with caution. Testbench and Verification

To verify the quarter-cycle offset, the testbench must monitor the transitions of both output channels and calculate the time delta between their rising edges. Use code with caution. Synthesis and Physical Design Considerations

When moving from RTL simulation to hardware implementation (FPGA/ASIC), observe these constraints:

Clock Distribution: High-frequency clock generators are highly sensitive to clock skew. Both clk_a and clk_b must be routed through global clock buffers (e.g., BUFG in Xilinx/AMD architectures) to minimize skew across the chip layout.

Static Timing Analysis (STA): You must define a false path or explicit multi-cycle path constraints if these two clocks interact across different logic domains. Use your STA tool to verify that setup and hold times are met at the 90-degree interface boundaries.

Alternative PLL Approach: For ultra-high-frequency applications where a 2x master clock is impractical, utilize internal Phase-Locked Loops (PLLs) or Mixed-Mode Clock Managers (MMCMs). Most modern FPGA hardware blocks offer dedicated primitives capable of outputting native 0° and 90° phase-shifted channels directly from a single reference clock. To tailor this code to your project, please let me know: What is your target master clock frequency? Are you synthesizing this for an FPGA or an ASIC target?

Do you require the two phases to be strictly non-overlapping (with dead time between phases)? Saved time Comprehensive Inappropriate Not working

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